The use of integrated circuits (ICs) with configurable circuits has dramatically increased in recent years. One example of an IC with configurable circuits is a field programmable gate array (FPGA). An FPGA is a field programmable IC that often has configurable logic circuits, configurable interconnect circuits, and non-configurable input/output (I/O) circuits. The logic circuits (also called logic blocks) are typically arranged as an internal array of circuits. These logic circuits are typically connected together through numerous interconnect circuits (also called interconnects). The logic and interconnect circuits are often surrounded by the I/O circuits which provide the interface between the internal FPGA components and components that exist outside the FPGA.
The configurable logic and configurable interconnect circuits of the FPGA are typically configured according to a user design. The user design specifies the operations to be performed by the one or more configurable logic circuits and the various interconnections needed to route the data to and from such circuits in a manner that performs the user design. However, a common limiting factor in the functionality of FPGAs and other ICs with configurable circuits are that the I/O circuits are not configurable. Rather, the I/O circuits are static in the sense that they optimally operate with a particular external interface specifying a specific operating voltage and operating frequency.
The peripheral component interconnect (PCI) standard specifies one such external interface. In a particular revision, the PCI interface specifies an operating voltage of 3.3V and an operating frequency of 133 MHz. Therefore, a configurable IC comprised of only non-configurable I/O circuits that optimally operate with the 3.3V PCI interface are limited to operating with interfaces that specify the same operational parameters as the PCI interface (i.e., 3.3V, 133 MHz), regardless of the virtually unlimited number of possible internal logic and interconnect configurations.
The use of the configurable IC, specifically the I/O circuits of the configurable IC, with any interface other than the interface for which the I/O circuits were designed to operate could cause physical or electrical damage to the I/O circuits or other components of the IC. For example, use of 3.3V interface specific I/O circuits with a 5V interface could cause oxide breakdown within the transistors/gates of the 3.3V I/O circuits and thereby cause physical damage to the gates/transistors. As a result, the non-configurable I/O circuits of an IC become a constraining factor to the broader applicability of the IC as the IC is constrained to operating with a single interface.
FIG. 1 presents a typical p-channel transistor (i.e., PMOS transistor) used in implementing part of an I/O circuit. The transistor of FIG. 1 includes a substrate region 110 composed of n-type semiconductor material which separates the source and drain regions 120 each doped with oppositely charged p-type semiconductor material. The transistor also includes a gate formed over a layer of silicon dioxide 140 that bridges the source and drain regions. By applying a charge to the gate 140, such as a positive voltage at the gate 140, negative charges are drawn up from the substrate 110 into the channel 130 and positive charges are forced away from the channel 130 as shown in FIG. 2.
As the charge on the gate 210 increases, more negative charges are attracted into the channel 130. The negative charges become distributed throughout the channel 130 to create an inversion layer through which a current may pass from the source and the drain 120. The current passing through the inversion layer increases as a voltage threshold (VTH) measuring the minimum voltage required to distribute the charges along the channel 130 is exceeded. Initially, the current across the channel 130 increases linearly until the transistor reaches a saturation state.
The linear increase of the current is determined through the following equation:IDL=μn*Cox*(W/L)*((VGS−VTH)*VDS−(V2DS/2))  (1)where ID equates to the current from source to drain, μn specifies the mobility of the charge carriers in the channel, Cox specifies the thickness of the gate oxide, W specifies the gate width, L specifies the gate length, VGS specifies the gate to source voltage, VTH specifies the threshold voltage of the transistor, and VDS specifies the drain to source voltage.
Saturation occurs when VGS exceeds VTH and VDS exceeds VGS less VTH. If VGS exceeds VDS, the current no longer increases linearly. Rather, the current passing through inversion layer is determined using the following equation:IDS=((μn*Cox)/2)*(W/L)*(VGS−VTH)2  (2)
Together equations (1) and (2) assist in determining a particular transistor's usefulness in operating with a particular external interface (i.e., operating voltage and operating frequency of the external interface). The I/O circuits, specifically the transistors comprising the I/O circuits, are said to be optimally operating with an interface when the transistors support a voltage of the interface while producing sufficient current to support the operating frequency specified by the interface.
FIG. 3 illustrates an output driver 300 for an I/O circuit found in the prior art. In FIG. 3, data and tri-state signals control the operation of the output driver 300 through a pair of level-shifting gates 310 and 320. The level-shifting OR gate 310 receives the complementary value of the data signal and the non-complementary value of the tri-state signal (i.e., the complementary tri-state signal passes through an inverter to restore the tri-state signal to its non-complementary value). These signals in conjunction with the OR gate 310 control the operation of PMOS transistor 330. The level-shifting AND gate 320 receives complementary values of both the data signal and tri-state signal in order to control the operation of NMOS transistor 340. Specifically, when the complementary value of the tri-state signal is high (i.e., active) and the complementary value of the data signal is low (i.e., inactive), the PMOS transistor 330 is closed and the NMOS transistor 340 is open thus allowing a current from a power source to be driven across the output path 350 at a specified voltage of a particular external interface. When both the complementary values of the tri-state and data signals are high, then the PMOS transistor 330 is open and the NMOS transistor 340 is closed causing the output of the output driver 300 to be grounded.
For an output driver 300 interfacing with a 3.3V interface, the output driver 300 would include a set 3.3V transistors for the transistors 330 and 340. This allows the output driver 300 to withstand the specified 3.3V of the interface and to produce a sufficient current for passing data through the interface at a specified frequency of the interface.
However, as mentioned above, a short coming of such prior art output drivers and I/O circuits is that these circuits are unable to adequately function over different interfaces. For example, application of an IC containing lower voltage circuits to a higher voltage interface results in electrical or physical damage to the I/O circuits as the smaller channel, thinner oxide layered transistors of the lower voltage I/O circuit cannot withstand the higher voltage. Similarly, application of an IC containing higher voltage I/O circuits to a lower voltage interface results in an insufficient current needed to propagate signals at a specified speed of the lower voltage interface. This occurs primarily because the voltage threshold for the transistors of the I/O circuit is only minimally exceeded resulting in the weak output current.
By modifying some of the characteristics of these transistors, the operating range of the transistors can be expanded to operate over a larger range of voltages or frequencies albeit with compromises to other properties of the transistor. Examples using the aforementioned equations (1) and (2) and other equations will now be given to illustrate the various compromises.
A transistor can be made to withstand larger operating voltage ranges by increasing the oxide thickness and the channel length of the transistor. However, increases to the oxide thickness and the channel length have the undesired effect of decreasing the current passing through the transistor. The tradeoff resulting from increasing oxide thickness is illustrated through the Cox variable of equations (1) and (2). In these equations, Cox represents the oxide thickness of the transistor. Cox is defined by the following equation:Cox=∈*A/d  (3)where ∈ specifies a dielectric constant, A specifies the area, and d specifies the oxide thickness. As the oxide thickness (i.e., variable d) increases, the value of Cox decreases causing the current drive, IDL or IDS, to similarly decrease. A similar tradeoff occurs between the channel length and the current drive. As evident in equations (1) and (2), this tradeoff is due to the inverse relationship between the current and the length of the transistor.
The decrease in current drive resulting from the increased oxide thickness and gate length can be offset through an increased gate width. Here again, a tradeoff results. In this instance, the size of the transistor increases causing the I/O circuit comprising the transistor to occupy additional surface area of the IC that could otherwise have been used to implement user logic or functionality. This also causes the parasitic capacitance to increase further resulting in a reduced operating frequency as shown below with reference to equation (9).
An example will now be given to illustrate the drop off in current that results from utilizing an I/O circuit with particular signaling parameters (e.g., operating voltage and/or operating frequency) for a particular interface in a different interface specifying a different set of signaling parameters. Equations (4) and (5) illustrate the current drop by solving the saturation equation (2) using signaling parameters of two different interfaces. First, equation (4) approximately computes the current produced when an I/O circuit comprising 3.3V transistors is applied to a 3.3V interface:K*(3.3−1)2=K*5.29  (4)where K is a fixed constant representing the properties of the 3.3V transistor ((μn*Cox)/2)* (W/L), 3.3 is the gate to source voltage (VGS) and 1 is the threshold voltage (VTH) for a 3.3V transistor.
Equation (5) approximately computes the current produced when the 3.3V transistors of the I/O circuit are applied to a 1.5V interface:K*(1.5−1)2=K*0.25  (5)Comparing the two results illustrates an approximate 20 to 1 drop in resulting current (5.29/0.25=21.16) when applying the I/O circuit with higher voltage transistors to a lower voltage interface (where K is constant since the same transistors are used to determine the current for two different interfaces).
Equations (6)-(8) illustrate a similar change that occurs to the output resistance of an I/O circuit by solving the linear region equation (1) using signaling parameters of two different interfaces. Equation (6) first illustrates an equation for computing the resistance based on the correspondence between resistance and current (i.e., R=V/I) and equation (1):R=1/(K*(VGS−VTH−(VDS/2)))  (6)
In equation (6), K is a fixed constant that represents the properties of a 3.3V transistor operating within the linear region (μn*Cox*W/L). From this equation, the changes to resistance for the given I/O circuit can be computed. Equation (7) approximately computes the resistance when an I/O circuit comprising 3.3V transistors having a 1V voltage threshold are applied to a 3.3V interface. Specifically, to compute equation (7), VDS is assumed to have a negligible value that does not affect the overall result:R=1/(K*(3.3−1))=0.435/K  (7)
Equation (8) approximately computes the resistance when the 3.3V transistors of the I/O circuit are applied to a 1.5V interface:R=1/(K*(1.5−1))=2/K  (8)Comparing the two results illustrates an approximate 5 to 1 change in resistance when the same transistors for the same I/O circuit are applied to two different interfaces.
Some ICs “finger” additional I/O circuits to a particular I/O circuit, where the particular I/O circuit comprises a single I/O circuit or multiple I/O circuits already within a fingered arrangement, in order to recover some of the lost current. Fingering involves connecting several I/O circuits in parallel. FIG. 4 illustrates the fingering of the output drivers of FIG. 3. Such a parallel placement of the I/O circuits 400 provides a linear gain in the strength of the current. However, the current is recuperated at the cost of a much larger I/O circuit 400 that occupies valuable surface area of the IC that could otherwise be used to provide additional user design functionality. Additionally, fingering increases the overall capacitance for the combined circuits. The increased capacitance results in a lower obtainable operating frequency as illustrated by the inverse relationship between frequency and capacitance in equation (9):F=1/(2*π*XC*C)  (9)where F specifies the frequency, XC specifies the inductive reactance, and C specifies the capacitance. As such, fingering is a not a viable option for producing an I/O circuit that optimally operates over two distinct frequencies and two distinct voltages.
Therefore, a need exists for a configurable I/O circuit that can configurably select from and optimally operate with multiple voltages while producing sufficient current at the voltages to support multiple operating frequencies. Also, a need exists for the configurable I/O circuit to provide such functionality while avoiding the increases in circuit size resulting from extraneous fingering of I/O circuits and the loss of operating frequency due to the increased capacitance of larger (i.e., wider) I/O circuits. Accordingly, the configurable I/O circuit should configurably support higher voltage lower speed interfaces while also configurably supporting lower voltage higher speed interfaces without increasing design complexity, size, or manufacturing complexity of the IC.